?2012 fairchild semiconductor corporation 1 www.fairchildsemi.com FSB50250US rev. c3 FSB50250US motion spm? 5 frfet? series april 2013 FSB50250US motion spm ? 5 frfet ? series features ? 500 v r ds(on) = 4.2 ( max ) frfet mosfet 3-phase inverter including hvics ? three separate negative dc-link terminals for inverter current sensing applications ? hvic for gate driving and undervoltage protection ? active-high interface, can work with 3.3 v / 5 v lo gic ? optimized for low electromagnetic interference ? isolation voltage rating of 1500 vrms for 1 min. ? surface mounted device package ? moisture sensitive level (msl) 3 applications ? 3-phase inverter driver for small power ac motor drives general description FSB50250US is an advanced motion spm5 series based on fast-recovery mosfet(frfet) technology as a compact inverter solution for small power motor drive applications such as fans and pumps. it is composed of six frfet mosfets and three half- bridge gate drive hvics. FSB50250US provides low electromagnetic interference(emi) characteristics wit h optimizing switching speed. moreover, since it employs mosfets as power switches, it has greater ruggedness and a larger safe operating area(soa) than igbt-based power modules. the pakage is optimized for thermal performance and compactness for use in applications where space is limited. FSB50250US is the right solution for inverters requir- ing energy efficiency, compactness, and low electro- manetic interference. related source ? an9042 : motion spm5 series ver.1 users guide ? an-9082 : motion spm5 series thermal performance by contact pressure package marking & ordering information device marking device package reel size packing type qua ntity FSB50250US FSB50250US spm5h-023 330 mm tape & reel 450
FSB50250US motion spm? 5 frfet? series ?2012 fairchild semiconductor corporation 2 www.fairchildsemi.com FSB50250US rev. c3 absolute maximum ratings inverter part (each mosfet ? unless otherwise specified) control part (each hvic unless otherwise specified) thermal resistance total system note: 1. for the measurement point of case temperature t c , please refer to figure 4. 2. marking * is calculation value or design f actor. symbol parameter conditions rating unit v pn dc link input voltage, drain-source voltage of each mosfet 500 v *i d 25 each mosfet drain current, continuous t c = 25c 1.1 a *i d 80 each mosfet drain current, continuous t c = 80c 0.8 a *i dp each mosfet drain current, peak t c = 25c, pw < 100 s 2.8 a *p d maximum power dissipation t c = 25c, for each mosfet 13 w symbol parameter conditions rating unit v cc control supply voltage applied between v cc and com 20 v v bs high-side bias voltage applied between v b and v s 20 v v in input signal voltage applied between in and com -0.3 ~ v cc +0.3 v symbol parameter conditions rating unit r jc junction to case thermal resistance each mosfet under inverter oper- ating condition (note 1) 9.3 c/w symbol parameter conditions rating unit t j operating junction temperature -40 ~ 150 c t stg storage temperature -40 ~ 125 c v iso isolation voltage 60 hz, sinusoidal, 1 minute, con- nection pins to heatsink 1500 v rms
FSB50250US motion spm? 5 frfet? series ?2012 fairchild semiconductor corporation 3 www.fairchildsemi.com FSB50250US rev. c3 pin descriptions note: source terminal of each low-side mosfet is not conn ected to supply ground or bias voltage ground insid e motion spm ? . external connections should be made as indicated in figure 3 figure 1. pin configuration and internal block dia gram (bottom view) pin number pin name pin description 1 com ic common supply ground 2 v b(u) bias voltage for u phase high side mosfet ? driving 3 v cc(u) bias voltage for u phase ic and low side mosfet dri ving 4 in (uh) signal input for u phase high-side 5 in (ul) signal input for u phase low-side 6 v s(u) bias voltage ground for u phase high side mosfet dr iving 7 v b(v) bias voltage for v phase high side mosfet driving 8 v cc(v) bias voltage for v phase ic and low side mosfet dri ving 9 in (vh) signal input for v phase high-side 10 in (vl) signal input for v phase low-side 11 v s(v) bias voltage ground for v phase high side mosfet dr iving 12 v b(w) bias voltage for w phase high side mosfet driving 13 v cc(w) bias voltage for w phase ic and low side mosfet dri ving 14 in (wh) signal input for w phase high-side 15 in (wl) signal input for w phase low-side 16 v s(w) bias voltage ground for w phase high side mosfet dr iving 17 p positive dcClink input 18 u output for u phase 19 n u negative dcClink input for u phase 20 n v negative dcClink input for v phase 21 v output for v phase 22 n w negative dcClink input for w phase 23 w output for w phase com vcc lin hin vb ho vs lo com vcc lin hin vb ho vs lo com vcc lin hin vb ho vs lo (1) com (2) v b(u) (3) v cc(u) (4) in (uh) (5) in (ul) (6) v s(u) (7) v b(v) (8) v cc(v) (9) in (vh) (10) in (vl) (11) v s(v) (12) v b(w) (13) v cc(w) (14) in (wh) (15) in (wl) (16) v s(w) (17) p (18) u (19) n u (20) n v (21) v (22) n w (23) w
FSB50250US motion spm? 5 frfet? series ?2012 fairchild semiconductor corporation 4 www.fairchildsemi.com FSB50250US rev. c3 electrical characteristics (t j = 25c, v cc =v bs = 15 v unless otherwise specified) inverter part (each mosfet ? unless otherwise specified) control part (each hvic unless otherwise specified) note: 1. bv dss is the absolute maximum voltage rating between dra in and source terminal of each mosfet inside motion spm ? . v pn should be sufficiently less than this value considering the effect of the stray inductance so t hat v ds should not exceed bv dss in any case. 2. t on and t off include the propagation delay time of the internal drive ic. listed values are measured at the labora tory test condition, and they can be different acco rding to the field applications due to the effect of diff erent printed circuit boards and wirings. please se e figure 4 for the switching time definition with t he switching test circuit of figure 5. 3. the peak current and voltage of each mosfet duri ng the switching operation should be included in th e safe operating area (soa). please see figure 5 fo r the rbsoa test circuit that is same as the switching test circuit. symbol parameter conditions min typ max unit bv dss drain-source breakdown voltage v in = 0v, i d = 1 ma (note 1) 500 - - v ? bv dss / ? t j breakdown voltage tem- perature coefficient i d = 250 a, referenced to 25c - 0.53 - v i dss zero gate voltage drain current v in = 0v, v ds = 500 v - - 250 a r ds(on) static drain-source on-resistance v cc = v bs = 15 v, v in = 5 v, i d = 0.5 a - 3.5 4.2 v sd drain-source diode forward voltage v cc = v bs = 15v, v in = 0v, i d = -0.5 a - - 1.2 v t on switching times v pn = 300 v, v cc = v bs = 15 v, i d = 0.5 a v in = 0 v ? 5 v, inductive load l= 3 mh high- and low-side mosfet switching (note 2) - 1050 - ns t off - 850 - ns t rr - 170 - ns e on - 40 - j e off - 10 - j rbsoa reverse-bias safe oper- ating area v pn = 400 v, v cc = v bs = 15 v, i d = i dp , v ds =bv dss , t j = 150c high- and low-side mosfet switching (note 3) full square symbol parameter conditions min typ max unit i qcc quiescent v cc current v cc =15 v, v in =0v applied between v cc and com - - 160 a i qbs quiescent v bs current v bs =15 v, v in =0v applied between v b(u) -u, v b(v) -v, v b(w) -w - - 100 a uv ccd low-side undervoltage protection (figure 6) v cc undervoltage protection detection level 7.4 8.0 9.4 v uv ccr v cc undervoltage protection reset level 8.0 8.9 9.8 v uv bsd high-side undervoltage protection (figure 7) v bs undervoltage protection detection level 7.4 8.0 9.4 v uv bsr v bs undervoltage protection reset level 8.0 8.9 9.8 v v ih on threshold voltage logic high level applied between in and com 3.0 - - v v il off threshold voltage logic low level - - 0.8 v i ih input bias current v in = 5v applied between in and com - 10 20 a i il v in = 0v - - 2 a
FSB50250US motion spm? 5 frfet? series ?2012 fairchild semiconductor corporation 5 www.fairchildsemi.com FSB50250US rev. c3 recommended operating condition note: 1. it is recommended the bootstrap diode d 1 to have soft and fast recovery characteristics wit h 600-v rating. 2. parameters for bootstrap circuit elements are dep endent on pwm algorithm. for 15 khz of switching fr equency, typical example of parameters is shown abo ve. 3. rc coupling (r 5 and c 5 ) at each input of motion spm ? and micom (indicated as dotted lines) may be used to prevent improper signal due to surge noise. 4. bold lines should be short and thick in pcb patte rn to have small stray inductance of circuit, which results in the reduction of surge voltage. bypass capacitors such as c 1 , c 2 and c 3 should have good high-frequency characteristics to absorb high-frequency ripple current. figure 2. recommended mcu interface and bootstrap circuit with parameters note: attach the thermocouple on top of the heatsink-side of motion spm (between motion spm and heatsink if applied) to get the correct temperature measurement . figure 3. case temperature measurement symbol parameter conditions value unit min. typ. max. v pn supply voltage applied between p and n - 300 400 v v cc control supply voltage applied between v cc and com 13.5 15 16.5 v v bs high-side bias voltage applied between v b and v s 13.5 15 16.5 v v in(on) input on threshold voltage applied between in and com 3.0 - v cc v v in(off) input off threshold voltage 0 - 0.6 v t dead blanking time for preventing arm-short v cc =v bs = 13.5 ~ 16.5 v, t j 150c 1.0 - - s f pwm pwm switching frequency t j 150c - 15 - khz hin lin output note 0 0 z both frfet off 0 1 0 low side frfet on 1 0 v dc high side frfet on 1 1 forbidden shoot through open open z same as (0,0) com vcc lin hin vb ho vs lo p n r 3 inverter output c 3 r 1 d 1 c 1 r 2 micom 15-v line 10 f one-leg diagram of spm these values depend on pwm control algorithm * example of bootstrap paramters: c 1 = c 2 = 1 f ceramic capacitor, r 1 = 56 , r 2 = 20 r 5 c 5 v dc c 2 case temperature(tc) detecting point 14.50mm 3.80mm mosfet case temperature(tc) detecting point 14.50mm 3.80mm mosfet
FSB50250US motion spm? 5 frfet? series ?2012 fairchild semiconductor corporation 6 www.fairchildsemi.com FSB50250US rev. c3 figure 4. switching time definitions figure 5. switching and rbsoa (single-pulse) test c ircuit (low-side) figure 6. undervoltage protection (low-side) figure 7. undervoltage protection (high-side) t on t rr i rr 100% of i d 120% of i d (a) turn-on t off (b) turn-off i d v ds v ds i d v in v in 10% of i d com vcc lin hin vb ho vs lo one-leg diagram of motion spm i d v cc r bs r eh c bs l v dc + v ds - uv ccd uv ccr input signal uv protection status low-side supply, v cc mosfet current reset detection reset uv bsd uv bsr input signal uv protection status high-side supply, v bs mosfet current reset detection reset
FSB50250US motion spm? 5 frfet? series ?2012 fairchild semiconductor corporation 7 www.fairchildsemi.com FSB50250US rev. c3 note: 1. about pin position, refer to figure 1. 2. rc coupling (r 5 and c 5 , r 4 and c 4 ) at each input of motion spm ? and micom are useful to prevent improper input sig nal caused by surge noise. 3. the voltage drop across r 3 affects the low side switching performance and the bootstrap characteristics since it is placed betwe en com and the source terminal of the low side mosfet. for this reason, the voltage drop across r 3 should be less than 1 v in the steady-state. 4. ground wires and output terminals, should be thi ck and short in order to avoid surge voltage and ma lfunction of hvic. 5. all the filter capacitors should be connected cl ose to motion spm, and they should have good charac teristics for rejecting high-frequency ripple curre nt. figure 8. example of application circuit com vcc lin hin vb ho vs lo com vcc lin hin vb ho vs lo com vcc lin hin vb ho vs lo (1) com (2) v b(u) (3) v cc(u) (4) in (uh) (5) in (ul) (6) v s(u) (7) v b(v) (8) v cc(v) (9) in (vh) (10) in (vl) (11) v s(v) (12) v b(w) (13) v cc(w) (14) in (wh) (15) in (wl) (16) v s(w) (17) p (18) u (19) n u (20) n v (21) v (22) n w (23) w micom c 1 r 1 r 2 15-v supply m c 3 v dc r 1 r 1 c 1 c 1 c 2 c 2 c 2 r 3 r 4 c 4 r 5 c 5 for 3-phase current sensing and protection
FSB50250US motion spm? 5 frfet? series ?2012 fairchild semiconductor corporation 8 www.fairchildsemi.com FSB50250US rev. c3 detailed package outline drawings #1 #16 17.90 12.30 2.80 15*1.778=26.67 1.30 13.34 0.30 15.60 7.80 4.43 2.48 land pattern recommendations 0.60 0.10 max 1.00 (1.165) 15*1.778=26.67 0.30 (-) (+) 12.00 0.20 29.00 0.20 0.60 0.10 max 1.00 (1.80) (1.30) (2.275) 4x3.90=15.60 0.30 1.95 #1 #16 #17 #23 2x3.90=7.80 0.30 0.508 0.15 +0.10 -0.15 5 3 1.50 0.20 (2.50) (1.30) gage plane max 3.50 12.23 0.30 13.13 0.30 13.34 0.30 seating plane (1.80) 3.10 0.20 (1.00) 17.00 0.20 0 . 5 0 + 0 . 1 0 - 0 . 0 5
FSB50250US motion spm? 5 frfet? series rev. i38 trademarks the following includes registered and unregistered trademarks and service marks, owned by fairchild se miconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trade marks. * ezswitch? and flashwriter ? are trademarks of system general corporation, used under license by fairchild semiconductor. disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products here in to improve reliability, function, or design. fairchild does no t assume any liability arising out of the applicati on or use of any product or circuit described herein; neither does i t convey any license under its patent rights, nor t he rights of others. these specifications do not expand the terms of fai rchilds worldwide terms and conditions, specifical ly the warranty therein, which covers these products. life support policy fairchilds products are not authorized for use as critical components in life support devices or syst ems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or s ystems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the u ser. 2. a critical component in any component of a life s upport, device, or system whose failure to perform can be reasonably e xpected to cause the failure of the life support device or system, o r to affect its safety or effectiveness. product status definitions definition of terms build it now? coreplus? corepower? crossvolt ? ctl? current transfer logic? ecospark ? efficentmax? ezswitch? * ? fairchild ? fairchild semiconductor ? fact quiet series? fact ? fast ? fastvcore? flashwriter ? * fps? f-pfs? frfet ? global power resource sm green fps? green fps? e-series? gto? intellimax? isoplanar? megabuck? microcoupler? microfet? micropak? millerdrive? motionmax? motion-spm? optologic ? optoplanar ? ? pdp spm? power-spm? powertrench ? powerxs? programmable active droop? qfet ? qs? quiet series? rapidconfigure? ? saving our world, 1mw /w /kw at a time? smartmax? smart start? spm ? stealth? superfet? supersot?-3 supersot?-6 supersot?-8 supremos? syncfet? ? the power franchise ? tinyboost? tinybuck? tinylogic ? tinyopto? tinypower? tinypwm? tinywire? trifault detect? serdes? uhc ? ultra frfet? unifet? vcx? visualmax? xs? ? datasheet identification product status definition advance information formative / in design datasheet contains the design specifications for pr oduct development. specifications may change in any manner without notice. preliminary first production datasheet contains preliminary data; supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice to improve design. no identification needed full production datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice to improve the design. obsolete not in production datasheet contains specifications on a product that is discontinued by fairchild semiconductor. the datasheet is for reference infor mation only. anti-counterfeiting policy fairchild semiconductor corporations anti-counterf eiting policy. fairchilds anti-counterfeiting poli cy is also stated on our external website, www.fairchildsemi.com, under sales support . counterfeiting of semiconductor parts is a growing problem in the industry. all manufactures of semico nductor products are experiencing counterfeiting of their parts. customers who inadvertently purchase counter feit parts experience many problems such as loss of brand reputation, substandard performance, failed application, and increased cost of production and m anufacturing delays. fairchild is taking strong mea sures to protect ourselves and our customers from t he proliferation of counterfeit parts. fairchild stron gly encourages customers to purchase fairchild part s either directly from fairchild or from authorized fairchild distributors who are listed by country on our web p age cited above. products customers buy either from fairchild directly or from authorized fairchild distributors are genuine parts, have full traceabil ity, meet fairchilds quality standards for handing and storage and provide access to fairchilds full range of up-to-date technical and product information. fairc hild and our authorized distributors will stand beh ind all warranties and will appropriately address a nd warranty issues that may arise. fairchild will not provide any warranty coverage or other assistance f or parts bought from unauthorized sources. fairchil d is committed to combat this global problem and encoura ge our customers to do their part in stopping this practice by buying direct or from authorized distri butors. ?2012 fairchild semiconductor corporation 9 www.fairchildsemi.com FSB50250US rev. c3
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